EDN

Implementing floating-point DSP on FPGAs

For developers using FPGAs for the implementation of floating-point DSP functions, one key challenge is how to decompose the computation algorithm into sequences of parallel hardware processes while ...
EDN

How to achieve 1 trillion floating-point operations-per-second in an FPGA

Based on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs. To date, virtually all FPGA-based signal ...
Electronic Design

PCs Bridge The Gap Between DSP And FPGA Designers

Typically, DSP designers are unfamiliar with FPGA design tools, and FPGA designers are unfamiliar with DSP algorithms. But when Sandia National Laboratories needed to replace an analog implementation ...
Design-Reuse

Altera Changes the Game for Floating Point DSP in FPGAs

San Jose, Calif., April 22, 2014– Altera Corporation (Nasdaq: ALTR) today changed the game as it relates to floating-point DSP performance in an FPGA. Altera is the first programmable logic company to ...
Design-Reuse

Altera Offers First C-code-based DSP Design Flow for FPGAs

San Jose, Calif., September 4, 2002 —Altera Corporation (NASDAQ: ALTR) today announced the availability of the FPGA industry's first C-code-based design flow for digital signal processing (DSP) ...